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“Crossfire helps CAD teams and IC designers achieve a predictable design flow by ensuring that every design step is validated and every imported IP-component is qualified,” says Rene Donkers, CEO of Fractal Technologies. The validation process spans through the full design flow from documentation to RTL to .lib and to gds. With the help of wide-ranging deep-submicron quality checks, the capability to support an exhaustive set of EDA formats and the ability to integrate customized checks through their API, Crossfire can adapt to any design flow and quality requirements.
Crossfire supports more than 20 different data formats to ensure there is no discrepancy in the design flow
Further, the tool offers robust usability features to ensure that the information represented across the various views is consistent. The usability features include waiving mechanism, reviewing and debugging, and graphical setup creation. With the help of Crossfire’s reporting feature, IC designers can report mismatches or modeling errors. Any error related to terminal names, conditional timing arcs or Boolean output terminal functionality is captured and flagged for the end-user with a graphical illustration. The QA reports generated by the tool in HTML format can be directly delivered to the IP-customer to demonstrate the integrity of the delivered IP block. Also, Crossfire’s integration feature offers an open API, using which customers can efficiently validate and visualize their scripts in-house. Thus, Fractal’s Crossfire acts both as a QA backbone and a one-stop shop for verification and validation of IP across the entire product lifecycle.
Additionally, IP typically comes with a pre-qualified set of specifications that must be maintained in the final design. Even the smallest mistake could easily invalidate the entire SoC. Addressing this issue is Fractal’s Transport feature that ensures IP block meets all the specification necessary for IP to qualify for the final phase of the development process. With such capabilities, Fractal Technologies is not only assisting chip development companies but also foundries, IDMs, independent IP design houses and fabless businesses in the area of design-flow, to have an end-of-line check before IP shipment or as an incoming inspection tool.
Moving forward, Fractal technologies is excited about its latest tools—bottleneck analysis and error fingerprints tools. Driven by the strong presence in the design ecosystem worldwide, the firm aims to become the de facto IP and library validation solutions provider for the semiconductors industry while staying independent to keep its intrinsic value by delivering comprehensive, easy-to-use, and flexible products.